Surface mounting electronic components, such as semiconductor chips, upon circuit boards or printed wiring boards has become popular. Typically, electronic component surface mounting is achieved through the controlled collapse of predetermined solder bumps or droplets. More particularly, predetermined arrays of solder bumps are arranged on conductive metal terminals of a semiconductor chip, or other electronic component to be surface mounted. Additionally, predetermined arrays of solder bumps are positioned on matching footprints of conductive terminals which are located on the surface of a predetermined circuit board. Thereafter, the electronic components are aligned upside down, i.e. face down on a circuit board. Heat is then applied to reflow the solder bumps into firm solid connections between such electronic components and the mating circuit board. Conductive adhesives may also be substituted for solder in a typical surface mounting process.
Widespread use of such surface mounting techniques has brought with it concerns over the reliability and integrity of the resulting adhesive and/or roller joints. In the past, joint cracking and other circuit board structural disturbances have been experienced, such as but not limited to, circuit board warping and structural failure of the electronic component itself. These structural disturbances are believed to be caused by the existence of unequal thermal coefficients of expansion vis-a-vis the electronic components to be mounted and the printed circuit boards. For example, when heat cycling is applied to reflow the solder, the electronic components and the circuit boards do not expand evenly across their own surfaces. This is true even if electronic components and circuit boards of equal thermal coefficients of expansion are utilized.
Various efforts have been employed to reduce the detrimental effects of such unequal thermal coefficients of expansion. Such efforts have included the following: modifying the solder array geometry by deleting comer solder bumps; using circular or other symmetrical arrays of solder bumps and contact pads; and physically supporting the electronic component by injecting an elastomeric support resin between the component and the circuit board. Other methods are described in U.S. Pat. Nos. 3,541,222; 3,934,959; 4,194,209; 4,847,146; 4,991,290, 5,046,953, and 5,049,084.
In U.S. Pat. No. 4,847,146, a process is disclosed for fabricating a compliant layer board with selectively isolated solder pads. In accordance with this process, an expansion layer is provided which includes a top surface and a bottom surface. The bottom surface of the expansion layer is bonded to a top surface of a support layer by way of an adhesive layer, except that the bottom surface of the expansion layer is not bonded to the support layer underneath an electronic component to be mounted. In theory, it is asserted that such a construction provides an expansion area wherein the expansion layer is free to expand and contract with an electronic component irrespective of the remainder of the printed circuit board.
Although the foregoing attempts to solve the problems in this area may have been met with varying degrees of success, they continue to suffer from a multiplicity of shortcomings which detract from their usefulness. For example, the process of U.S. Pat. No. 4,847,146 may require a manufacturer of printed circuit boards to customize the expansion layer of each board, which may be extremely costly and time consuming. Also, the expansion area discussed in U.S. Pat. No. 4,847,146 may attract process chemicals, debris and/or moisture which may eventually lead to premature structural failure of the circuit board or the electronic component.
Accordingly, there exists a continuing need to provide a stress-resistant circuit board which mitigates structural degradation of the circuit board caused by uneven thermal expansion between a circuit board and any electrical components mounted thereupon.